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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16602-1E
32-bit Microcontroller
CMOS
FR60 MB91460 Series
MB91461
DESCRIPTION
MB91461 is a line of the general-purpose 32-bit RISC microcontrollers designed for embedded control applications such as consumer devices and vehicle system, which require high-speed real-time processing. MB91461 uses the FR60 CPU compatible with the FR family* CPUs. MB91461 contains the LIN-UART and CAN controller. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
FEATURES
* FR60 CPU * 32-bit RISC, load/store architecture, five-stage pipeline * Maximum operating frequency : 80 MHz (oscillation frequency 20 MHz, oscillation frequency 4 multiplier (PLL clock multiplication method)) * 16-bit fixed-length instructions (basic instructions) * Instruction execution speed : 1 instruction per cycle * Instructions including memory-to-memory transfer, bit manipulation instructions, and barrel shift instructions: Instructions suitable for embedded applications * Function entry/exit instructions and register data multi load store instructions: Instructions supporting C language * Register interlock function : Facilitating assembly-language coding * Built-in multiplier with instruction-level support Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interrupt (PC/PS saving) : 6 cycles (16 priority levels) (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2007 FUJITSU LIMITED All rights reserved
MB91460 Series
* Harvard architecture enabling simultaneous execution of both program access and data access * Instructions compatible with the FR family * Internal peripheral resources * MB91461 does not contain the ROM and flash memory. * Internal RAM capacity : Instruction cache 4 Kbytes + 64 Kbytes (Instruction/data common RAM) * General-purpose port : Maximum 72 ports * DMAC (DMA Controller) Maximum of 5 channels for simultaneous operation is possible. (1 channel for external-to-external) 3 transfer sources (external pin/internal peripheral/software) Activation source can be selected using software. Addressing mode with 32-bit full address indication (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Fly-by transfer support (between external I/O and memory) Transfer data size selection 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) * A/D converter (sequential comparison) 10-bit resolution: 13 channels Conversion time: 1 s (peripheral macro operation clock at 16.67 MHz) * External interrupt input: 16 channels Pins shared with RX pins of CAN0 and CAN1 * Bit search module (for REALOS) Function of searching for the first "0" data/ "1" data/change bit position in 1 word from the MSB (upper bit) * LIN-UART (full duplex double buffer): 7 channels Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator * I2C* bus interface (400 kbps supported): 3 channels Master/slave sending and receiving Arbitration function, clock synchronization function * CAN controller (C-CAN) : 2 channels Maximum transfer speed : 1 Mbps 32 sent/received message buffers * 16-bit PPG timer : 8 channels * 16-bit reload timer : 5 channels * 16-bit free-run timer : 4 channels (1 channel each for ICU and OCU) * Input capture : 4 channels (work with free-run timer) * Output compare : 4 channels (work with free-run timer) * Watchdog timer Watchdog reset output pin available * Real-time clock * Low-power consumption mode: Sleep/stop/shutdown mode function (Continued)
2
MB91460 Series
(Continued) * Package : LQFP-176 (FPT-176P-M07) * CMOS 0.18 m technology * 3 V/5 V power supplies [Internal logic is kept at 1.8 V by step-down circuit, some I/Os have the withstand voltage of 5.0 V] * Operating temperature range : between - 40C and + 85C * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
3
MB91460 Series
PIN ASSIGNMENT
(TOP VIEW)
VCC5 P17_3/PPG3 P17_2/PPG2 P17_1/PPG1 P17_0/PPG0 P14_3/ICU3/TIN3/TRG3 P14_2/ICU2/TIN2/TRG2 P14_1/ICU1/TIN1/TRG1 P14_0/ICU0/TIN0/TRG0 P22_3 P22_2/INT13 P22_0/INT12 P23_6/INT11 P23_4/INT10 VCC5 VSS P15_3/OCU3/TOT3 P15_2/OCU2/TOT2 P15_1/OCU1/TOT1 P15_0/OCU0/TOT0 P18_2/SCK6 P18_1/SOT6 P18_0/SIN6 P19_6/SCK5 P19_5/SOT5 P19_4/SIN5 P19_2/SCK4 P19_1/SOT4 P19_0/SIN4 VCC5 VSS P20_6/SCK3/FRCK3 P20_5/SOT3 P20_4/SIN3 P20_2/SCK2/FRCK2 P20_1/SOT2 P20_0/SIN2 P21_6/SCK1/FRCK1 P21_5/SOT1 P21_4/SIN1 P21_2/SCK0/FRCK0 P21_1/SOT0 P21_0/SIN0 VCC5 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
VSS P24_2/INT2 P24_3/INT3 P22_6/SDA1/INT15 P22_7/SCL1 P24_4/SDA2/INT4 P24_5/SCL2/INT5 DREQ0 DACK0 DEOP0 VCC3 VCC3 VSS C_1 CS4 CS3 CS2 CS1 CS0 IORD IOWR RDY BRQ BGRNT RD WR0 WR1 SYSCLK AS VCC3 C_2 VSS X0 X1 VSS D16 D17 D18 D19 D20 D21 D22 D23 VCC3
(1)
(2)
(3)
VSS INIT TRST MD0 MD1 MD2 MD3 P23_3/TX1 P23_2/RX1/INT9 P23_1/TX0 P23_0/RX0/INT8 P24_7/INT7 P24_6/INT6 P22_5/SCL0 P22_4/SDA0/INT14 P24_1/INT1 P24_0/INT0 AVRH AVCC3 AVSS/AVRL P28_4/AN12 P28_3/AN11 P28_2/AN10 P28_1/AN9 P28_0/AN8 P29_7/AN7 P29_6/AN6 P29_5/AN5 P29_4/AN4 P29_3/AN3 P29_2/AN2 P29_1/AN1 P29_0/AN0 WDRESET BREAK ICLK ICS2 ICS1 ICS0 ICD3 ICD2 ICD1 ICD0 VCC3
Note : (1) to (3) are 3.3 V/5 V pin supported pin, and can set 3.3 V and 5 V to the voltage in each block. I2C pin in (1) can be inputted at 5 V power supply. However, 3.3 V of the input threshold value is used as the standard value regardless of the power supply voltage. If 5 V is set in (1) or (2), also set 5 V to (3).
4
VSS D24 D25 D26 D27 D28 D29 D30 D31 A00 A01 A02 VCC3 VSS A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 VCC3 VSS A17 A18 A19 A20 A21 A22 A23 NMI P16_7/ATG P17_4/PPG4 P17_5/PPG5 P17_6/PPG6 P17_7/PPG7 VSS
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
(FPT-176P-M07)
MB91460 Series
PIN DESCRIPTION
Pin no. 2 3 Pin name P24_2 INT2 P24_3 INT3 P22_6 4 SDA1 INT15 5 P22_7 SCL1 P24_4 6 SDA2 INT4 P24_5 7 8 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 33 34 SCL2 INT5 DREQ0 DACK0 DEOP0 CS4 CS3 CS2 CS1 CS0 IORD IOWR RDY BRQ BGRNT RD WR0 WR1 SYSCLK AS X0 X1 I O O O O O O O O O I I O O O O O O H H H H H H H H H H H H H H H H H H G G I/O Open Drain C I/O Open Drain C I/O Open Drain C I/O Open Drain C I/O I/O I/O I/O circuit type* D D Function General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port I2C bus data input/output pin External interrupt input pin General-purpose input/output port I2C bus clock input/output pin General-purpose input/output port I2C bus data input/output pin External interrupt input pin General-purpose input/output port I2C bus clock input/output pin External interrupt input pin DMA external transfer request input DMA external transfer acknowledge output DMA external transfer EOP (End of Process) output Chip select 4 output Chip select 3 output Chip select 2 output Chip select 1 output Chip select 0 output Read strobe output at DMA fly-by transfer Write strobe output at DMA fly-by transfer External ready input External bus open request input External bus open acknowledge output External read strobe output External write strobe output External write strobe output System clock output Address strobe output Clock (oscillation) input Clock (oscillation) output (Continued) 5
MB91460 Series
Pin no. 36 to 43 46 to 53 54 to 56 59 to 72 75 to 81 82 83 84 to 87 90 to 93 94 to 96 97 98 99 100 to 107 108 to 112
Pin name D16 to D31
I/O I/O
I/O circuit type* H
Function External data bus signal
A00 to A23 NMI P16_7 ATG P17_4 to P17_7 PPG4 to PPG7 ICD0 to ICD3 ICS0 to ICS2 ICLK BREAK WDRESET P29_0 to P29_7 AN0 to AN7 P28_0 to P28_4 AN8 to AN12 P24_0, P24_1
O I I/O I/O I/O O O I O I/O I/O
H H H H H H I H J F F
External address bus signal NMI (Non Maskable Interrupt) input General-purpose input/output port A/D converter external trigger input General-purpose input/output ports PPG timer output pins Data input/output pins for development tool Status output pins for development tool Clock output pin for development tool Break input pin for development tool Watchdog reset output pin General-purpose input/output ports Analog input pins for A/D converter General-purpose input/output ports Analog input pins for A/D converter General-purpose input/output ports External interrupt input pins. Can be used as a return source from shutdown. General-purpose input/output port I2C bus data input/output pin External interrupt input pin General-purpose input/output port I2C bus clock input/output pin General-purpose input/output port External interrupt input pin. Can be used as a return source from shutdown. General-purpose input/output port External interrupt input pin. Can be used as a return source from shutdown. (Continued)
116, 117
INT0, INT1 P22_4
I/O
D
118
SDA0 INT14 P22_5 SCL0 P24_6
I/O Open Drain I/O Open Drain I/O
C
119
C
120
INT6 P24_7
D
121
INT7
I/O
D
6
MB91460 Series
Pin no.
Pin name P23_0
I/O
I/O circuit type* RX input pin of CAN0
Function General-purpose input/output port
122
RX0 INT8
I/O
D
External interrupt input pin. Can be used as a return source from shutdown. I/O D General-purpose input/output port TX output pin of CAN0 General-purpose input/output port I/O D RX input pin of CAN1 External interrupt input pin. Can be used as a return source from shutdown. I/O I I I I I I I/O I/O D A A A B E B D D Reset input pin for development tool External reset input General-purpose input/output port Data input pin of UART0 General-purpose input/output port Data output pin of UART0 General-purpose input/output port I/O D Clock input/output pin of UART0 External clock input pin of free-run timer0 I/O I/O D D General-purpose input/output port Data input pin of UART1 General-purpose input/output port Data output pin of UART1 General-purpose input/output port I/O D Clock input/output pin of UART1 External clock input pin of free-run timer1 I/O D General-purpose input/output port Data input pin of UART2 (Continued) Mode setting pins General-purpose input/output port TX output pin of CAN1
123
P23_1 TX0 P23_2 RX1 INT9
124
125 126 127 128 129 130 131 134 135
P23_3 TX1 MD3 MD2 MD1 MD0 TRST INIT P21_0 SIN0 P21_1 SOT0 P21_2 SCK0 FRCK0 P21_4 SIN1 P21_5 SOT1 P21_6 SCK1 FRCK1 P20_0 SIN2
136
137 138
139
140
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MB91460 Series
Pin no. 141
Pin name P20_1 SOT2 P20_2 SCK2 FRCK2 P20_4 SIN3 P20_5 SOT3 P20_6 SCK3 FRCK3 P19_0 SIN4 P19_1 SOT4 P19_2 SCK4 P19_4 SIN5 P19_5 SOT5 P19_6 SCK5 P18_0 SIN6 P18_1 SOT6 P18_2 SCK6 P15_0 to P15_3
I/O I/O
I/O circuit type* D
Function General-purpose input/output port Data output pin of UART2 General-purpose input/output port Clock input/output pin of UART2 External clock input pin of free-run timer2 General-purpose input/output port Data input pin of UART3 General-purpose input/output port Data output pin of UART3 General-purpose input/output port Clock input/output pin of UART3 External clock input pin of free-run timer3 General-purpose input/output port Data input pin of UART4 General-purpose input/output port Data output pin of UART4 General-purpose input/output port Clock input/output pin of UART4 General-purpose input/output port Data input pin of UART5 General-purpose input/output port Data output pin of UART5 General-purpose input/output port Clock input/output pin of UART5 General-purpose input/output port Data input pin of UART6 General-purpose input/output port Data output pin of UART6 General-purpose input/output port Clock input/output pin of UART6 General-purpose input/output ports Output compare output pins Reload timer output pins General-purpose input/output port External interrupt input pin (Continued)
142
I/O
D
143 144
I/O I/O
D D
145
I/O
D
148 149 150 151 152 153 154 155 156
I/O I/O I/O I/O I/O I/O I/O I/O I/O
D D D D D D D D D
157 to 160 OCU0 to OCU3 TOT0 to TOT3 163 P23_4 INT10
I/O
D
I/O
D
8
MB91460 Series
(Continued) Pin no. 164 165 166 167 Pin name P23_6 INT11 P22_0 INT12 P22_2 INT13 P22_3 P14_0 to P14_3 168 to 171 ICU0 to ICU3 TIN0 to TIN3 TRG0 to TRG3 172 to 175 P17_0 to P17_3 PPG0 to PPG3 I/O D I/O D I/O I/O I/O I/O I/O I/O circuit type* D D D D Function General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port General-purpose input/output ports Input capture input pins External trigger input pins of reload timer External trigger input pins of PPG General-purpose input/output ports PPG timer output pins
*: For details of I/O circuit types, refer to " I/O CIRCUIT TYPE".
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MB91460 Series
[Power supply/GND pins] Pin number Pin name 1, 13, 32, 35, 45, 58, 74, 88, 132, 146, 161 11, 12, 30, 44, 57, 73, 89 VSS
I/O (VSS) GND pins
Function
VCC3
(VCC3)
3.3 V power supply pins 5 V power supply pins. These pins are I/O power supplies corresponding to 116 to 145 pins. The corresponding I/O pin operates at 3.3 V when supplying 3.3 V, and at 5 V when supplying 5V. Be sure to supply 5 V if more than one 5V operating pin is specified, or 5V is supplied at pin 162 or pin 176. 5 V power supply pin. This pin is an I/O power supply corresponding to 148 to 160 pins. The corresponding I/O pin operates at 3.3 V when supplying 3.3 V, and at 5V when supplying 5 V. Be sure to supply 5 V if more than one 5 V operating pin is specified. 5 V power supply pin. This pin is an I/O power supply corresponding to 2 to 7 pins. The corresponding I/O pin operates at 3.3 V when supplying 3.3 V, and at 5 V when supplying 5 V. Be sure to supply 5 V if more than one 5 V operating pin is specified. Analog GND pin for A/D converter 3.3 V power supply pin for A/D converter Reference power supply pin for A/D converter Capacitor connection pin for internal regulator. Connect a 4.8 F capacitor. Capacitor connection pin for internal regulator. Connect a 4.8 F capacitor.
133, 147
VCC5
(VCC5)
162
VCC5
(VCC5)
176
VCC5
(VCC5)
113 114 115 14 31
AVSS/AVRL AVCC3 AVRH C_1 C_2
(AVSS) (AVCC3) (AVRH)
10
MB91460 Series
I/O CIRCUIT TYPE
Type 5 V level Input A
N-ch
Circuit type
Remarks 5 V CMOS hysteresis input
5 V CMOS hysteresis input
P-ch
B Input 5 V level Input/output pin for I2C IOL = 3 mA With stand voltage of 5 V With standby control
N-ch
Output drive N-ch C Input Standby control
(Continued)
11
MB91460 Series
Type
P-ch
Circuit type
Remarks 5 V CMOS output IOL = 4 mA 5 V CMOS input 5 V CMOS hysteresis input With 50 k pull-up/pull-down control With standby control
Pull-up control
P-ch
5 V level
N-ch
Output drive P-ch Output drive N-ch
D
N-ch
Pull-down control
Input Standby control Input Standby control 3.3 V level E Input 3.3 V CMOS hysteresis input With stand voltage of 5 V With standby control 3.3 V CMOS output IOL = 4 mA 3.3 V CMOS input 3.3 V CMOS hysteresis input Analog input With standby control
P-ch
3.3 V level
N-ch
Output drive P-ch Output drive N-ch
F
Input Standby control Input Standby control Analog input (Continued)
12
MB91460 Series
(Continued) Type 3.3 V level Input
Circuit type
Remarks 3.3 V oscillation cell
G
Standby control
P-ch
Pull-up control
P-ch
3.3 V level
N-ch
Output drive P-ch Output drive N-ch
3.3 V CMOS output IOL = 4 mA 3.3 V CMOS input 3.3 V CMOS hysteresis input With 33 k pull-up/pull-down control With standby control
H
N-ch
Pull-down control
Input Standby control Input Standby control 3.3 V CMOS output I : IOL = 8 mA J : IOL = 4 mA
P-ch
3.3 V level I, J
N-ch
Output drive P-ch
Output drive N-ch
13
MB91460 Series
HANDLING DEVICES
* Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage higher than VCC or less than VSS is applied to an input or output pin or if a voltage exceeding the rating is applied between VCC pin and VSS pin. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, when using a CMOS IC, do not exceed the maximum rating. * Handling of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor. * Power supply pins When provided with multiple VCC pins or VSS pins, the device is designed such that the pins having equal potential are interconnected internally to prevent malfunctions such as latch-up. All of these pins must however be connected to the power supply and ground externally to reduce unwanted radiation, to prevent the strobe signal from malfunctioning due to a rise of ground level, and to follow the total output current standards. In addition, VCC pin and VSS pin of this device should be connected from the power supply source with the lowest possible impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between VCC pin and VSS pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 F to C_1 and C_2 pins for the regulator. * Crystal oscillator circuit Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Printed circuit boards should be designed so that the X0 and X1 pins, and crystal oscillator, as well as bypass capacitors connected to ground, are placed as close together as possible. The use of printed circuit board architecture in which the X0 and X1 pins are surrounded by ground contributes to stable operation and is strongly recommended. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. * Notes on using external clock In principle, when using external clock, supply a clock to the X0 pin and X1 pin simultaneously. Also, an opposite phase clock to the X0 pin must be supplied to the X1 pin. However, in this case the stop mode (oscillation stop mode) must not be used (This is because the X1 pin stops at "H" output in STOP mode).
X0 X1
(Note) Stop mode (oscillation stop mode) cannot be used. Example of using external clock (normal)
14
MB91460 Series
* Mode pins (MD0 to MD3) When using mode pins, connect them directly to VCC pin or VSS pin. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and VCC pin or VSS pin on the printed circuit board as possible and connect them with low impedance. * Power-on sequences for 3.3 V and 5 V * Immediately after power-on, keep "L" level input to the INIT pin for the oscillation stabilization wait time (8 ms) to ensure the oscillation stabilization wait time for the oscillator circuit. * There is no power-on sequences. * When executing a reset cancellation (changing INIT pin from "L" level to "H" level), be sure to execute it while 3 V and 5 V power supplies are stable. * Caution on operations during PLL clock mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. * External bus setting This model guarantees the maximum frequency of 40 MHz for the external bus clock SYSCLK. Setting the base clock frequency to 80 MHz without changing the initial value of DIVR1 (external bus base clock division setting register) sets the external bus frequency also to 80 MHz. Before changing the base clock frequency, set SYSCLK not exceeding 40 MHz. * Pull-up control Connecting a pull-up resistor to the pin serving as an external bus pin cannot guarantee the AC standard. * Notes on PS register Since some instructions process the PS register in advance, the following exceptional operations may cause a break in the interrupt process routine or an update of display contents of the flag in the PS register when the debugger is being used. In either case, as the device is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified. 1) The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S instruction accepts a user interrupt/NMI, executes a step, or breaks in response to a data event or emulator menu. -D0 and D1 flags are updated in advance. -An EIT process routine (user interrupt/NMI or emulator) is executed. -Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as those in 1). 2) The following operations are performed when each instruction of OR CCR, ST ILM, MOV Ri and PS is executed to enable interrupts while a user interrupt/NMI source has been occurring. -The PS register is updated in advance. -An EIT process routine (user interrupt/NMI or emulator) is executed. -Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as that in 1).
15
MB91460 Series
NOTES ON DEBUGGER
* Step execution of RETI instruction In the environment where interrupts occur frequently when stepping, only the corresponding interrupt process routines are executed repeatedly. As the result of that, the main routine and low-interrupt-level programs are not executed (For example, if an interrupt to the time base timer is enabled, a break always occurs at the beginning of the time base routine when stepping RETI) . Disable the corresponding interrupts when the debug on the corresponding interrupt process routines becomes unnecessary. * Break function If the target address of a hardware break (including an event break) is set to the address currently contained in the system stack pointer or in the area containing the stack pointer, the user program causes a break after execution of one instruction even though there is no actual data access instruction in the user program. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of a hardware break (including an event break). * Operand break If a stack pointer exists in the area which is set as the DSU operand break, malfunctions may occur. Do not set the access to the areas containing the address of system stack pointer as a target of data event break.
16
MB91460 Series
DSU4 (ICE) DEDICATED CONNECTION PINS
MB91461 DSU4 (ICE) dedicated connection pins Pin no. Pin name 93 to 90 96 to 94 97 98 130 ICD3 to ICD0 ICS2 to ICS0 ICLK BREAK TRST Function Data input/output pins for development tool Status output pins for development tool Clock pin for development tool Break pin for development tool Reset pin for development tool (3 V/5 V supported input pin)
* User target side connector and the MB91461 connection The recommended connector for the user target side is shown below. Manufacturer : YAMAICHI ELECTRONICS CO., LTD. Model number : FAP-20-08#* Note : The asterisk (*) in the model number represents each of the following pin shapes: * 1 : Right angle/wrapping * 2 : Right angle/solder dip * 4 : Straight/solder dip
Pin 19
Pin 1
Pin 20
Pin 2
17
MB91460 Series
Connector pin no. 1 2 3 4 6 8 5 7 9 10 11 12 13 14 15 16 17 18 19 20
Signal line name EVCC2 EVCC3 DSUIO UVCC XRSTIN PLVL XTRST XINIT GND BREAK ICD3 ICD2 ICD1 ICD0 GND ICS2 ICS1 ICS0 GND ICLK
I/O I I I/O O O I I I I Open Open Open User VCC output
Pin handling
Connected to user circuit INIT signal Open Connected to TRST (130 pin) Connected to INIT (131 pin) Connected to VSS Connected to BREAK (98 pin) Connected to ICD3 (93 pin) Connected to ICD2 (92 pin) MB91461 Connected to ICD1 (91 pin) Connected to ICD0 (90 pin) Connected to VSS Connected to ICS2 (96 pin) Connected to ICS1 (95 pin) Connected to ICS0 (94 pin) Connected to VSS Connected to ICLK (97 pin)
I/O
O O
18
MB91460 Series
Handling of dedicated pin for DSU4 (ICE) in mass production Handling of dedicated pin for DSU4 (ICE) in mass production MB91461 pin no. Pin name 93 to 90 96 to 94 97 98 130 ICD3 to ICD0 ICS2 to ICS0 ICLK BREAK TRST Open Open Open Open Connected to INIT (131 pin: external reset input pin)
Pin handling
Connection handling of the reset pin (TRST) for development tool (DSU) in mass production
INIT MB91461 TRST
Reset input
Since the reset pin (TRST) for development tool is the input pin supporting 3V/5V, it can be connected to INIT pin directly.
19
MB91460 Series
BLOCK DIAGRAM
TRST BREAK ICS0 to ICS2 ICD0 to ICD3 ICLK
DSU (debug support)
FR60 CPU core Bit search
Instruction cache 4 Kbytes
I-bus 32 D-bus 32
CAN 2 channels 32 16 bus adapter
RX0,RX1 TX0,TX1
RAM 64 Kbytes
Bus converter
External bus interface
SYSCLK AS RD WR0 WR1 BRQ BGRNT CS0 to CS4 A23 to A00 D31 to D16
DREQ0 DACK0 DEOP0 IOWR IORD
DMAC 5 channels
R-bus 16
Interrupt controller Clock control
TRG0 to TRG3 PPG0 to PPG7 TIN0 to TIN3 TOT0 to TOT3 FRCK0 to FRCK3
PPG 8 channels Reload timer 5 channels Free-run timer 4 channels Input capture 4 channels Output compare 4 channels
External interrupt 16 channels PORT interface
LIN-UART 7 channels (including BGR)
NMI INT0 to INT15 PORT SIN0 to SIN6 SOT0 to SOT6 SCK0 to SCK6 SDA0 to SDA2 SCL0 to SCL2
ICU0 to ICU3
I2C 3 channels RTC
OCU0 to OCU3
A/D converter 13 channels
AN0 to AN12 ATG
: Pin for development tool
20
MB91460 Series
CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for embedded applications.
1. Features
* Adoption of RISC architecture Basic instruction: 1 instruction per cycle * General-purpose registers: 32-bit x 16 registers * 4 Gbytes linear memory space * Multiplier installed 32-bit x 32-bit multiplication: 5 cycles 16-bit x 16-bit multiplication: 3 cycles * Enhanced interrupt processing function Quick response speed (6 cycles) Multiple-interrupt support Level mask function (16 levels) * Enhanced instructions for I/O operation Memory-to-memory transfer instruction Bit processing instruction * Basic instruction word length: 16 bits * Low-power consumption Sleep mode/stop mode/shutdown mode
21
MB91460 Series
2. Internal architecture
The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. A 32-bit 16-bit bus adapter is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources. A Harvard Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the bus controller. The following figure shows the internal architecture structure.
DSU (debug support)
FR60 CPU core Bit search
Instruction cache RAM
I-bus 32 D-bus 32
CAN 2 channels 32 16 bus adapter
RAM 64 Kbytes
Bus converter
R-bus 16
External bus interface DMAC 5 channels Peripheral resource
22
MB91460 Series
3. Programming model
* Basic programming model 32 bits Initial value
R0 R1 ... ... ... ... XXXX XXXXH ... ... ... ... AC FP SP ... XXXX XXXXH 0000 0000H
General-purpose registers
R12 R13 R14 R15
Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiply and divide result registers
PC RS TBR RP SSP USP MDH MDL ILM SCR CCR
23
MB91460 Series
4. Registers
* General-purpose register
32 bits Initial value
R0 R1 ... ... R12 R13 R14 R15 AC FP SP ... ... XXXX XXXXH ... ... ... ... ... XXXX XXXXH 0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value). * PS (Program Status) This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The read values are always "0". Write access to these bits is invalid. Bit position bit 31
bit 20 bit 16 bit 10 bit 8 bit 7 bit 0
ILM
SCR
CCR
24
MB91460 Series
* CCR (Condition Code Register)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
- - 00XXXXB
S
I
N
Z
V
C
S I Z V
: Stack flag : Interrupt enable flag : Zero flag : Overflow flag
N : Negative enable flag
C : Carry flag * SCR (System Condition Register)
bit 10 bit 9 bit 8
Initial value
XX0B
D1
D0
T
Flag for step multiplication (D1, D0) This flag stores interim data during execution of step multiplication. Step trace trap flag (T) This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs. * ILM
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
01111B
ILM4 ILM3 ILM2 ILM1 ILM0
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking. The register is initialized to value "01111B" at reset. * PC (Program Counter)
bit 31 bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed. The initial value at reset is undefined.
25
MB91460 Series
* TBR (Table Base Register)
bit 31 bit 0
Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing. The initial value at reset is 000FFC00H. * RP (Return Pointer)
bit 31 bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to PC. The initial value at reset is undefined. * USP (User Stack Pointer)
bit 31 bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is "1", this register functions as the R15 register. * The USP register can also be explicitly specified. The initial value at reset is undefined. * This register cannot be used with RETI instructions. * Multiply & divide registers
bit 31 MDH MDL bit 0
These registers are for multiplication and division, and are each 32 bits in length. The initial value at reset is undefined.
26
MB91460 Series
MODE SETTING
In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating mode.
1. Mode pins
The three pins MD2, MD1, MD0 are used to specify the mode vector fetch related settings. Settings other than shown in the table are not allowed. Mode pins* Reset vector Mode name access area MD2 MD1 MD0 0 0 0 0 0 1 Internal ROM mode vector External ROM mode vector Internal External Not allowed Bus width is set by mode register.
Remarks
* : Always use MD3 with "0". Note : The FR family does not support the external mode vector fetch using multiplex bus.
2. Mode register (MODR)
The data written to the mode register using mode vector fetch is called mode data. After the mode register (MODR) is set, the device operates according to the operation mode set in this register. The mode register is set by all reset sources. User programs cannot write data to the mode register. Rewriting is allowed in the emulator mode. In this case, use an 8-bit length data transfer instruction. A 16/32-bit length transfer instruction cannot be used for writing. Description of the mode register is given below. [Mode register description]
bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 ROMA bit 1 WTH1 bit 0 WTH0
Initial value
XXXXXXXXB
Operation mode setting bits
[bit7 to bit3] Reserved bits Be sure to set these bits to "00000B". Operation is not guaranteed when any value other than "00000B" is set. [bit2] ROMA (Internal enable bit) The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas. ROMA Function Remarks 0 1 External ROM mode Internal ROM mode Internal F-bus RAM becomes valid. The internal ROM area (40000H to FFFFFH) is used as an external area. Internal F-bus RAM and F-bus ROM become valid.
Note : Use "0" in MB91461.
27
MB91460 Series
[bit1, bit0] WTH1, WTH0 (Bus width setting bits) These bits are used to set the bus width to be used in the external bus mode. When the operation mode is the external bus mode, these values are set in bits BW1 and BW0 in AMD0 (CS0 area). WTH1 WTH0 Function Remarks 0 0 1 1 0 1 0 1 8-bit bus width 16-bit bus width Single chip mode External bus mode External bus mode Setting disabled Setting disabled
28
MB91460 Series
MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. * Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH
2. Memory map
MB91461 External ROM External bus mode
0000 0000H I/O 0000 0400H
Direct addressing area Refer to " I/O MAP".
I/O
0000 8000H 0000 BFFFH
BI-ROM I/O
0001 0000H 0002 0000H 0003 0000H 0004 0000H
Instruction cache
F-bus RAM
External area
Reset/vector mode
0010 0000H
External area
FFFF FFFFH
: Access prohibited
Each mode is set depending on the mode vector fetch after INIT is negated. (For details on mode settings, refer to " MODE SETTING".) 29
MB91460 Series
I/O MAP
Address 000000H Register +0 PDR0 [R/W]B XXXXXXXX +1 PDR1 [R/W]B XXXXXXXX +2 PDR2 [R/W]B XXXXXXXX +3 PDR3 [R/W]B XXXXXXXX Block
T-unit port data register
Read/write attribute, Access unit (B: Byte, H: Half word, W: Word) Register initial value after reset Register name (column 1 register at address 4n, column 2 register at address 4n + 1...) Leftmost register address (for word access, the register in column 1 becomes the MSB side of the data.)
Note : Initial values of register bits are represented as follows: " 1 " : Initial value " 1 " " 0 " : Initial value " 0 " " X " : Initial value " undefined " " - " : No physical register at this location Access is barred with an undefined data access attribute.
30
MB91460 Series
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H 000024H to 00002CH 000030H
Register 0 1 Reserved Reserved Reserved Reserved PDR14 [R/W] B,H PDR15 [R/W] B,H ----XXXX ----XXXX 2 3
Block
PDR16 [R/W] B,H PDR17 [R/W] B,H PDR18 [R/W] B,H PDR19 [R/W] B,H X------XXXXXXXX -----XXX -XXX-XXX PDR20 [R/W] B,H PDR21 [R/W] B,H PDR22 [R/W] B,H PDR23 [R/W] B,H -XXX-XXX -XXX-XXX XXXXXX-X -X-XXXXX PDR24 [R/W] B,H XXXXXXXX PDR28 [R/W] B,H PDR29 [R/W] B,H ---XXXXX XXXXXXXX Reserved Reserved Reserved
R-bus port data register
Reserved
Reserved External interrupt (INT0 to INT7) NMI External interrupt (INT 8 to INT15 ) Delay interrupt Reserved RDR00/TDR00 [R/W] B,H,W 00000000 UART (LIN) 0 Reserved
EIRR0 [R/W] B 00000000 EIRR1 [R/W] B 00000000 DICR [R/W] B -------0
ENIR0 [R/W] B 00000000 ENIR1 [R/W] B 00000000 HRCL [R/W] B 0--11111 Reserved
ELVR0 [R/W] B,H 00000000 00000000 ELVR1 [R/W] B,H 00000000 00000000 Reserved
000034H 000038H 00003CH 000040H
SCR00 [R/W,W] B,H,W 00000000 ESCR00 [R/W] B,H 00000X00 SCR01 [R/W,W] B,H,W 00000000 ESCR01 [R/W] B,H 00000X00
SMR00 [R/W,W] B,H,W 00000000 ECCR00 [R/W,R,W] B,H -00000XX SMR01 [R/W,W] B,H,W 00000000 ECCR01 [R/W,R,W] B,H -00000XX
SSR00 [R/W,R] B,H,W 00001000
000044H
000048H
SSR01 [R/W,R] B,H,W 00001000
RDR01/TDR01 [R/W] B,H,W 00000000
LIN-UART 1
00004CH
Reserved (Continued) 31
MB91460 Series
Address
Register 0 SCR02 [R/W,W] B,H,W 00000000 ESCR02 [R/W]B,H 00000X00 SCR03 [R/W,W] B,H,W 00000000 ESCR03 [R/W] B,H 00000X00 SCR04 [R/W,W] B,H,W 00000000 ESCR04 [R/W] B,H,W 00000X00 SCR05 [R/W,W] B,H,W 00000000 ESCR05 [R/W] B,H,W 00000X00 SCR06 [R/W,W] B,H,W 00000000 ESCR06 [R/W] B,H,W 00000X00 1 SMR02 [R/W,W] B,H,W 00000000 ECCR02 [R/W,R,W] B,H -00000XX SMR03 [R/W,W] B,H,W 00000000 ECCR03 [R/W,R,W] B,H -00000XX SMR04 [R/W,W] B,H,W 00000000 ECCR04 [R/W,R,W] B,H,W -00000XX SMR05 [R/W,W] B,H,W 00000000 ECCR05 [R/W,R,W] B,H,W -00000XX SMR06 [R/W,W] B,H,W 00000000 ECCR06 [R/W,R,W] B,H,W -00000XX 2 SSR02 [R/W,R] B,H,W 00001000 3 RDR02/TDR02 [R/W] B,H,W 00000000
Block
000050H
LIN-UART 2
000054H
Reserved SSR03 [R/W,R] B,H,W 00001000 RDR03/TDR03 [R/W] B,H,W 00000000
000058H
LIN-UART 3
00005CH
Reserved SSR04 [R/W,R] B,H,W 00001000 FSR04 [R] B,H,W ---00000 SSR05 [R/W,R] B,H,W 00001000 FSR05 [R] B,H,W ---00000 SSR06 [R/W,R] B,H,W 00001000 FSR06 [R] B,H,W ---00000 RDR04/TDR04 [R/W] B,H,W 00000000 FCR04 [R/W] B,H,W 0001-000 RDR05/TDR05 [R/W] B,H,W 00000000 FCR05 [R/W] B,H,W 0001-000 RDR06/TDR06 [R/W] B,H,W 00000000 FCR06 [R/W] B,H,W 0001-000
000060H
LIN-UART 4
000064H
000068H
LIN-UART 5
00006CH
000070H
LIN-UART 6
000074H 000078H to 00007CH 000080H
Reserved BGR100 [R/W] B,H,W 00000000 BGR102 [R/W] B,H,W 00000000 BGR104 [R/W] B,H,W 00000000 BGR000 [R/W] B,H,W 00000000 BGR002 [R/W] B,H,W 00000000 BGR004 [R/W] B,H,W 00000000 BGR101 [R/W] B,H,W 00000000 BGR103 [R/W] B,H,W 00000000 BGR105 [R/W] B,H,W 00000000 BGR001 [R/W] B,H,W 00000000 BGR003 [R/W] B,H,W 00000000 BGR005 [R/W] B,H,W 00000000
Reserved
000084H
Baud rate generator UART (LIN) 0 to 6
000088H
(Continued)
32
MB91460 Series
Address
Register 0 BGR106 [R/W] B,H,W 00000000 1 BGR006 [R/W] B,H,W 00000000 2 3
Block Baud rate generator UART (LIN) 0 to 6 Reserved
00008CH
Reserved
000090H to 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H to 0000FCH 000100H 000104H 000108H 000110H PTMR00 [R] H 11111111 11111111 PDUT00 [W] H XXXXXXXX XXXXXXXX PTMR01 [R] H 11111111 11111111 PDUT01 [W] H XXXXXXXX XXXXXXXX PTMR02 [R] H 11111111 11111111 PDUT02 [W] H XXXXXXXX XXXXXXXX GCN10 [R/W] B,H 00110010 00010000 GCN11 [R/W] B,H 00110010 00010000 IBCR0 [R/W] B,H 00000000
Reserved IBSR0 [R] B,H 00000000 ITBAH0 [R/W] B,H ITBAL0 [R/W] B,H ------00 00000000 ISMK0 [R/W] B,H 01111111 ICCR0 [R/W] B -0011111 ISBA0 [R/W] B,H -0000000 Reserved
ITMKH0 [R/W] B,H ITMKL0 [R/W] B,H 00----11 11111111 Reserved IBCR1 [R/W] B,H 00000000 IDAR0 [R/W] B,H 00000000 IBSR1 [R] B,H 00000000
I2C 0
ITBAH1 [R/W] B,H ITBAL1 [R/W] B,H ------00 00000000 ISMK1 [R/W] B,H 01111111 ICCR1 [R/W] B -0011111 ISBA1 [R/W] B,H -0000000 Reserved I2C 1
ITMKH1 [R/W] B,H ITMKL1 [R/W] B,H 00----11 11111111 Reserved IDAR1 [R/W] B,H 00000000
Reserved GCN20 [R/W] B ----0000 GCN21 [R/W] B ----0000
Reserved PPG control 0 to 3 PPG control 4 to 7 Reserved PCSR00 [W] H XXXXXXXX XXXXXXXX
Reserved Reserved Reserved
000114H
PCNH00 [R/W] B,H 00000000
PCNL00 [R/W] B,H 000000-0
PPG 0
000118H
PCSR01 [W] H XXXXXXXX XXXXXXXX PCNH01 [R/W] B,H 00000000 PCNL01 [R/W] B,H 000000-0 PPG 1
00011CH
000120H
PCSR02 [W] H XXXXXXXX XXXXXXXX PCNH02 [R/W] B,H 00000000 PCNL02 [R/W] B,H 000000-0 PPG 2
000124H
(Continued) 33
MB91460 Series
Address 000128H
Register 0 1 2 3 PTMR03 [R] H 11111111 11111111 PDUT03 [W] H XXXXXXXX XXXXXXXX PTMR04 [R] H 11111111 11111111 PDUT04 [W] H XXXXXXXX XXXXXXXX PTMR05 [R] H 11111111 11111111 PDUT05 [W] H XXXXXXXX XXXXXXXX PTMR06 [R] H 11111111 11111111 PDUT06 [W] H XXXXXXXX XXXXXXXX PTMR07 [R] H 11111111 11111111 PDUT07 [W] H XXXXXXXX XXXXXXXX PCSR03 [W] H XXXXXXXX XXXXXXXX PCNH03 [R/W] B,H 00000000 PCNL03 [R/W] B,H 000000-0
Block
PPG 3
00012CH
000130H
PCSR04 [W] H XXXXXXXX XXXXXXXX PCNH04 [R/W] B,H 00000000 PCNL04 [R/W] B,H 000000-0 PPG 4
000134H
000138H
PCSR05 [W] H XXXXXXXX XXXXXXXX PCNH05 [R/W] B,H 00000000 PCNL05 [R/W] B,H 000000-0 PPG 5
00013CH
000140H
PCSR06 [W] H XXXXXXXX XXXXXXXX PCNH06 [R/W] B,H 00000000 PCNL06 [R/W] B,H 000000-0 PGG 6
000144H
000148H
PCSR07 [W] H XXXXXXXX XXXXXXXX PCNH07 [R/W] B,H 00000000 Reserved PCNL07 [R/W] B,H 000000-0 PPG 7
00014CH 000170H to 00017CH 000180H 000184H 000188H 00018CH 000190H 000194H
Reserved ICS23 [R/W] B 00000000 Input capture 0 to 3
Reserved
ICS01 [R/W] B 00000000
Reserved
IPCP0 [R] H XXXXXXXX XXXXXXXX IPCP2 [R] H XXXXXXXX XXXXXXXX OCS01 [R/W] 11101100 00001100 OCCP0 [R/W] H XXXXXXXX XXXXXXXX OCCP2 [R/W] H XXXXXXXX XXXXXXXX
IPCP1 [R] H XXXXXXXX XXXXXXXX IPCP3 [R] H XXXXXXXX XXXXXXXX OCS23 [R/W] 11101100 00001100 OCCP1 [R/W] H XXXXXXXX XXXXXXXX OCCP3 [R/W] H XXXXXXXX XXXXXXXX
Output compare 0 to 3
(Continued)
34
MB91460 Series
Address 000198H to 00019CH 0001A0H 0001A4H 0001A8H 0001ACH 0001B0H
Register 0 1 Reserved ADERH [R/W] B,H,W 00000000 00000000 ADCS1 [R/W] B,H ADCS0 [R/W] B,H 00000000 00000000 ADERL [R/W] B,H,W 00000000 00000000 ADCR1 [R] B,H 000000XX ADCR0 [R] B,H XXXXXXXX 2 3
Block
Reserved
A/D converter
ADCT1 [R/W] B,H ADCT0 [R/W] B,H ADSCH [R/W] B,H ADECH [R/W] B,H 00010000 00101100 ---00000 ---00000 Reserved TMRLR0 [W] H XXXXXXXX XXXXXXXX Reserved TMRLR1 [W] H XXXXXXXX XXXXXXXX Reserved TMRLR2 [W] H XXXXXXXX XXXXXXXX Reserved TMRLR3 [W] H XXXXXXXX XXXXXXXX Reserved TMR0 [R] H XXXXXXXX XXXXXXXX TMCSRC0 [R/W] B,H ---00000 TMCSRC0 [R/W] B,H 0-000000 Reserved
0001B4H
Reload timer 0 (PPG 0, 1)
0001B8H
TMR1 [R] H XXXXXXXX XXXXXXXX TMCSRC1 [R/W] B,H ---00000 TMCSRC1 [R/W] B,H 0-000000
0001BCH
Reload timer 1 (PPG 2, 3)
0001C0H
TMR2 [R] H XXXXXXXX XXXXXXXX TMCSRC2 [R/W] B,H ---00000 TMCSRC2 [R/W] B,H 0-000000
0001C4H
Reload timer 2 (PPG 4, 5)
0001C8H
TMR3 [R] H XXXXXXXX XXXXXXXX TMCSRC3 [R/W] B,H ---00000 Reserved TMCSRC3 [R/W] B,H 0-000000
0001CCH 0001D0H to 0001E4H 0001E8H
Reload timer 3 (PPG 6, 7)
Reserved TMR7 [R] H XXXXXXXX XXXXXXXX
TMRLR7 [W] H XXXXXXXX XXXXXXXX Reserved
0001ECH
TMCSRC7 [R/W] B,H ---00000 Reserved
TMCSRC7 [R/W] B,H 0-000000 TCCS0 [R/W] -0000000
Reload timer 7 (A/D converter)
0001F0H
TCDT0 [R/W] H XXXXXXXX XXXXXXXX
Free-run timer 0 (ICU 0, 1) (Continued) 35
MB91460 Series
Address
Register 0 1 2 Reserved 3 TCCS1 [R/W] -0000000 TCCS2 [R/W] -0000000 TCCS3 [R/W] -0000000
Block Free-run timer 1 (ICU 2, 3) Free-run timer 2 (OCU 0, 1) Free-run timer 3 (OCU 2, 3)
0001F4H
TCDT1 [R/W] H XXXXXXXX XXXXXXXX TCDT2 [R/W] H XXXXXXXX XXXXXXXX TCDT3 [R/W] H XXXXXXXX XXXXXXXX
0001F8H 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 000254H 000258H to 000364H
Reserved Reserved
DMACA0 [R/W] B,H,W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] B,H,W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] B,H,W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] B,H,W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] B,H,W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] B,H,W 00000000 00000000 XXXXXXXX XXXXXXXX Reserved DMACR [R/W] B,H,W 00--0000 Reserved Reserved Reserved (Continued) DMAC
Reserved
36
MB91460 Series
Address 000368H 00036CH 000370H 000374H to 0003BCH 0003C0H 0003C4H 0003D0H 0003E4H 0003E8H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H to 00043CH 000440H
Register 0 IBCR2 [R/W] B,H 00000000 1 IBSR2 [R] B,H 00000000 2 3 ITBAH2 [R/W] B,H ITBAL2 [R/W] B,H ------00 00000000 ISBA2 [R/W] B,H -0000000 Reserved
Block
ITMKH2 [R/W] B,H ITMKL2 [R/W] B,H ISMK2 [R/W] B,H 00----11 11111111 01111111 Reserved IDAR2 [R/W] B,H 00000000 ICCR2 [R/W] B -0011111
I2C 2
Reserved Reserved Reserved Reserved Reserved Reserved ICHRC [R/W] B 0-000000 Reserved BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved ICR00 [R/W] B,H,W ---11111 ICR04 [R/W] B,H,W ---11111 ICR08 [R/W] B,H,W ---11111 ICR12 [R/W] B,H,W ---11111 ICR01 [R/W] B,H,W ---11111 ICR05 [R/W] B,H,W ---11111 ICR09 [R/W] B,H,W ---11111 ICR13 [R/W] B,H,W ---11111 ICR02 [R/W] B,H,W ---11111 ICR06 [R/W] B,H,W ---11111 Reserved ICR03 [R/W] B,H,W ---11111 ICR07 [R/W] B,H,W ---11111 ICR11 [R/W] B,H,W ---11111 Reserved (Continued) 37 Reserved ISIZE [R/W] B ------11 Instruction cache Reserved Instruction cache
Reserved
Bit search module
000444H
Interrupt controller
000448H
00044CH
MB91460 Series
Address
Register 0 ICR16 [R/W] B,H,W ---11111 ICR20 [R/W] B,H,W ---11111 Reserved 1 Reserved ICR21 [R/W] B,H,W ---11111 ICR25 [R/W] B,H,W ---11111 ICR29 [R/W] B,H,W ---11111 Reserved ICR38 [R/W] B,H,W ---11111 ICR42 [R/W] B,H,W ---11111 Reserved ICR48 [R/W] B,H,W ---11111 ICR49 [R/W] B,H,W ---11111 ICR50 [R/W] B,H,W ---11111 ICR51 [R/W] B,H,W ---11111 ICR39 [R/W] B,H,W ---11111 ICR43 [R/W] B,H,W ---11111 ICR22 [R/W] B,H,W ---11111 ICR26 [R/W] B,H,W ---11111 2 3 ICR19 [R/W] B,H,W ---11111 ICR23 [R/W] B,H,W ---11111 ICR27 [R/W] B,H,W ---11111
Block
000450H
000454H
000458H
00045CH
Reserved
Reserved
000460H
000464H
Reserved
Interrupt controller
000468H
Reserved
00046CH
000470H
000474H
Reserved ICR58 [R/W] B,H,W ---11111 ICR62 [R/W] B,H,W ---11111 TBCR [R/W] B,H,W X0000X00 DIVR0 [R/W] B,H,W 00000011 ICR59 [R/W] B,H,W ---11111 ICR63 [R/W] B,H,W ---11111 CTBR [W] B,H,W XXXXXXXX DIVR1 [R/W] B,H,W 00000000 Clock control
000478H
Reserved
00047CH
Reserved RSRR [R/W] B,H,W 10000000 CLKR [R/W] B,H,W 00000000 STCR [R/W] B,H,W 00110011 WPR [W] B,H,W XXXXXXXX
000480H
000484H
000488H
Reserved
Reserved (Continued)
38
MB91460 Series
Address
Register 0 PLLDIVM [R/W] B,H ---00000 1 PLLDIVN [R/W] B,H ---00000 Reserved 2 Reserved 3
Block
00048CH 000490H 000494H to 00049CH 0004A0H 0004A4H 0004A8H 0004ACH to 0004BCH 0004C0H
PLL interface
Reserved Reserved WTCER [R/W] B,H ------00 WTCR [R/W] B,H 00000000 000-00-0 Real-time clock
Reserved Reserved WTHR [R/W] B,H ---XXXXX
WTBR [R/W] B, B,H ---XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] B,H --XXXXXX WTSR [R/W] B --XXXXXX Reserved
Reserved CANPRE [R/W] B,H 00000000 Reserved OSCR [R/W] B,H 00---000 Reserved
Reserved
Reserved HWDCS [R/W,W] B 00011000 Reserved
CAN (clock control) Hardware watchdog Interval timer Reserved
0004C4H
0004C8H 0004CCH 0004D0H 0004D4H 0004D8H 0004DCH to 00063CH 000640H 000644H 000648H 00064CH
Reserved SHDE [R/W] B 0------Reserved EXTE [R/W] B,H 00000000 EXTF [R/W] B,H 00000000 Shutdown controller
EXTLV [R/W] B,H 00000000 00000000 Reserved ASR0 [R/W] B,H,W 00000000 00000000 ASR1 [R/W] B,H,W XXXXXXXX XXXXXXXX ASR2 [R/W] B,H,W XXXXXXXX XXXXXXXX ASR3 [R/W] B,H,W XXXXXXXX XXXXXXXX
Reserved
Reserved ACR0*2 [R/W] B,H,W 1111XX00 00000000 ACR1 [R/W] B,H,W XXXXXXXX XXXXXXXX ACR2 [R/W] B,H,W XXXXXXXX XXXXXXXX ACR3 [R/W] B,H,W XXXXXXXX XXXXXXXX (Continued) 39
External bus
MB91460 Series
Address 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H 000688H to 0007F8H 0007FCH 000800H to 000CFCH 000D00H 000D04H 000D08H 000D0CH 000D10H
Register 0 1 2 3 ASR4 [R/W] B,H,W XXXXXXXX XXXXXXXX Reserved Reserved Reserved AWR0 [R/W] B,H,W 01111111 11111011 AWR2 [R/W] B,H,W XXXXXXXX XXXXXXXX AWR4 [R/W] B,H,W XXXXXXXX XXXXXXXX Reserved Reserved Reserved IOWR0 [R/W] B,H,W XXXXXXXX CSER [R/W] B,H,W 00000001 IOWR1 [R/W] B,H,W XXXXXXXX CHER [R/W] B,H,W 11111111 Reserved Reserved MODR [W] B XXXXXXXX Reserved Reserved Reserved Reserved Reserved PDRD16 [R] B,H X------PDRD17 [R] B,H XXXXXXXX PDRD14 [R] B,H ----XXXX PDRD18 [R] B,H -----XXX PDRD15 [R] B,H ----XXXX PDRD19 [R] B,H -XXX-XXX IOWR2 [R/W] B,H,W XXXXXXXX Reserved AWR1 [R/W] B,H,W XXXXXXXX XXXXXXXX AWR3 [R/W] B,H,W XXXXXXXX XXXXXXXX Reserved ACR4 [R/W] B,H,W XXXXXXXX XXXXXXXX
Block
External bus
Reserved Reserved TCR [R/W]*3 B,H,W 0000XXXX
Reserved
Reserved
Mode register
Reserved
R-bus port data direct read register
(Continued)
40
MB91460 Series
Address 000D14H 000D18H 000D1CH 000D20H 000D24H to 000D3CH 000D40H 000D44H 000D48H 000D4CH 000D50H 000D54H 000D58H 000D5CH 000D60H 000D64H to 000D7CH 000D80H 000D84H 000D88H 000D8CH 000D90H
Register 0 PDRD20 [R] B,H -XXX-XXX PDRD24 [R] B,H XXXXXXXX PDRD28 [R] B,H ---XXXXX PDRD29 [R] B,H XXXXXXXX Reserved 1 PDRD21 [R] B,H -XXX-XXX 2 PDRD22 [R] B,H XXXXXX-X Reserved Reserved 3 PDRD23 [R] B,H -X-XXXXX
Block
R-bus port data direct read register
Reserved Reserved Reserved Reserved Reserved DDR14 [R/W] B,H DDR15 [R/W] B,H ----0000 ----0000
Reserved
DDR16 [R/W] B,H DDR17 [R/W] B,H DDR18 [R/W] B,H DDR19 [R/W] B,H 0------00000000 -----000 -000-000 DDR20 [R/W] B,H DDR21 [R/W] B,H DDR22 [R/W] B,H DDR23 [R/W] B,H -000-000 -000-000 000000-0 -0-00000 DDR24 [R/W] B,H ---00000 DDR28 [R/W] B,H DDR29 [R/W] B,H ---00000 00000000 Reserved Reserved Reserved
R-bus port direction register
Reserved
Reserved
Reserved Reserved Reserved Reserved PFR16 [R/W] B,H 0------PFR17 [R/W] B,H 00000000 PFR14 [R/W] B,H ----0000 PFR18 [R/W] B,H -----000 PFR15 [R/W] B,H ----0000 PFR19 [R/W] B,H -000-000 (Continued) 41 R-bus port function register
MB91460 Series
Address 000D94H 000D98H 000D9CH 000DA0H 000DA4H to 000DBCH 000DC0H 000DC4H 000DC8H
Register 0 PFR20 [R/W] B,H -000-000 PFR24 [R/W] B,H 00000000 PFR28 [R/W] B,H ---00000 1 PFR21 [R/W] B,H -000-000 Reserved PFR29 [R/W] B,H 00000000 Reserved Reserved 2 PFR22 [R/W] B,H 000000-0 Reserved Reserved 3 PFR23 [R/W] B,H -0-00000 Reserved Reserved
Block
R-bus port function register
Reserved
Reserved Reserved Reserved EPFR14 [R/W] B,H ----0000 EPFR18 [R/W] B,H -----000 EPFR22 [R/W] B,H 000000-0 Reserved EPFR29 [R/W] B,H 00000000 Reserved EPFR15 [R/W] B,H ----0000 EPFR19 [R/W] B,H -000-000 EPFR23 [R/W] B,H -0-00000 R-bus expansion port function register
000DCCH
Reserved EPFR16 [R/W] B,H 0------EPFR20 [R/W] B,H -000-000 EPFR24 [R/W] B,H 00000000 EPFR28 [R/W] B,H ---00000 EPFR17 [R/W] B,H 00000000 EPFR21 [R/W] B,H -000-000
000DD0H
000DD4H
000DD8H
000DDCH
Reserved
000DE0H 000DE4H to 000DFCH 000E00H to 000E3CH
Reserved Reserved Reserved (Continued)
42
MB91460 Series
Address 000E40H 000E44H 000E48H 000E4CH 000E50H 000E54H 000E58H 000E5CH 000E60H to 000EBCH 000EC0H 000EC4H 000EC8H
Register 0 1 Reserved Reserved Reserved Reserved PILR14 [R/W] B,H PILR15 [R/W] B,H ----0000 ----0000 2 3
Block
PILR16 [R/W] B,H PILR17 [R/W] B,H PILR18 [R/W] B,H PILR19 [R/W] B,H 0------00000000 -----000 -000-000 PILR20 [R/W] B,H PILR21 [R/W] B,H PILR22 [R/W] B,H PILR23 [R/W] B,H -000-000 -000-000 000000-0 -0-00000 PILR24 [R/W] B,H 00000000 PILR28 [R/W] B,H PILR29 [R/W] B,H ---00000 00000000 Reserved Reserved Reserved
R-bus pin input level selection register
Reserved Reserved Reserved PPER14 [R/W] B,H ----0000 PPER18 [R/W] B,H -----000 PPER22 [R/W] B,H 000000-0 Reserved PPER29 [R/W] B,H 00000000 Reserved (Continued) 43 PPER15 [R/W] B,H ----0000 PPER19 [R/W] B,H -000-000 PPER23 [R/W] B,H -0-00000 R-bus port pull-up/pull-down enable register
000ECCH
Reserved PPER16 [R/W] B,H 0------PPER20 [R/W] B,H -000-000 PPER24 [R/W] B,H 00000000 PPER28 [R/W] B,H ---00000 PPER17 [R/W] B,H 00000000 PPER21 [R/W] B,H -000-000
000ED0H
000ED4H
000ED8H
000EDCH
Reserved
000EE0H
MB91460 Series
Address 000EE4H to 000EFCH 000F00H 000F04H 000F08H
Register 0 1 Reserved 2 3
Block
Reserved
Reserved Reserved Reserved PPCR14 [R/W] B,H ----1111 PPCR18 [R/W] B,H 111111-1 PPCR22 [R/W] B,H 111111-1 Reserved PPCR29 [R/W] B,H 11111111 Reserved PPCR15 [R/W] B,H ----1111 PPCR19 [R/W] B,H -1-11111 PPCR23 [R/W] B,H -1-11111 R-bus port pull-up/pull-down control register
000F0CH
Reserved PPCR16 [R/W] B,H 1------PPCR20 [R/W] B,H -111-111 PPCR24 [R/W] B,H ---11111 PPCR28 [R/W] B,H ---11111 PPCR17 [R/W] B,H -111-111 PPCR21 [R/W] B,H -111-111
000F10H
000F14H
000F18H
000F1CH
Reserved
000F20H 000F24H to 000F3CH 001000H 001004H 001008H 00100CH 001010H 001014H
Reserved DMASA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
DMAC
(Continued) 44
MB91460 Series
Address 001018H 00101CH 001020H 001024H 001028H to 007FFCH 008000H to 00BFFCH 00C000H 00C004H 00C008H 00C00CH 00C010H 00C014H 00C018H 00C01CH 00C020H 00C024H 00C028H to 00C02CH 00C030H 00C034H
Register 0 1 2 3 DMASA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved
Block
DMAC
Reserved Reserved CTRLR0 [R/W] B,H 00000000 00000001 ERRCNT0 [R] B,H,W 00000000 00000000 INTR0 [R]B,H,W 00000000 00000000 BRPE0 [R/W]B,H,W 00000000 00000000 IF1CREQ0 [R/W] B,H 00000000 00000001 IF1MSK20 [R/W] B,H,W 11111111 11111111 IF1ARB20 [R/W] B,H,W 00000000 00000000 IF1MCTR0 [R/W] B,H,W 00000000 00000000 IF1DTA10 [R/W] B,H,W 00000000 00000000 IF1DTB10 [R/W] B,H,W 00000000 00000000 Reserved IF1DTA20 [R/W] B,H,W 00000000 00000000 IF1DTB20 [R/W] B,H,W 00000000 00000000 IF1DTA10 [R/W] B,H,W 00000000 00000000 IF1DTB10 [R/W] B,H,W 00000000 00000000 (Continued) 45 STATR0 [R/W] B,H 00000000 00000000 BTR0 [R/W] B,H,W 00100011 00000001 TESTR0 [R/W]B,H,W 00000000 X0000000 Reserved IF1CMSK0 [R/W] B,H 00000000 00000000 IF1MSK10 [R/W] B,H,W 11111111 11111111 IF1ARB10 [R/W] B,H,W 00000000 00000000 Reserved IF1DTA20 [R/W] B,H,W 00000000 00000000 IF1DTB20 [R/W]B,H,W 00000000 00000000 CAN 0 IF 1 register CAN 0 control register
MB91460 Series
Address 00C038H to 00C03CH 00C040H 00C044H 00C048H 00C04CH 00C050H 00C054H 00C058H to 00C05CH 00C060H 00C064H 00C068H to 00C07CH 00C080H 00C084H 00C088H 00C08CH 00C090H 00C094H 00C098H 00C09CH
Register 0 1 Reserved IF2CREQ0 [R/W] B,H 00000000 00000001 IF2MSK20 [R/W] B,H,W 11111111 11111111 IF2ARB20 [R/W] B,H,W 00000000 00000000 IF2MCTR0 [R/W] B,H,W 00000000 00000000 IF2DTA10 [R/W] B,H,W 00000000 00000000 IF2DTB10 [R/W] B,H,W 00000000 00000000 Reserved IF2DTA20 [R/W] B,H,W 00000000 00000000 IF2DTB20 [R/W] B,H,W 00000000 00000000 Reserved TREQR20 [R] B,H,W 00000000 00000000 Reserved Reserved Reserved NEWDT20 [R] B,H,W 00000000 00000000 Reserved Reserved Reserved NEWDT10 [R] B,H,W 00000000 00000000 TREQR10 [R] B,H,W 00000000 00000000 IF2DTA10 [R/W] B,H,W 00000000 00000000 IF2DTB10 [R/W] B,H,W 00000000 00000000 IF2CMSK0 [R/W] B,H 00000000 00000000 IF2MSK10 [R/W] B,H,W 11111111 11111111 IF2ARB10 [R/W] B,H,W 00000000 00000000 Reserved IF2DTA20 [R/W] B,H,W 00000000 00000000 IF2DTB20 [R/W] B,H,W 00000000 00000000 2 3
Block CAN 0 IF 1 register
CAN 0 IF 2 register
CAN 0 status flag
(Continued) 46
MB91460 Series
Address 00C0A0H 00C0A4H 00C0A8H 00C0ACH 00C0B0H 00C0B4H 00C0B8H 00C0BCH 00C0C0H to 00C0FCH 00C100H 00C104H 00C108H 00C10CH 00C110H 00C114H 00C118H 00C11CH 00C120H 00C124H
Register 0 1 2 3 INTPND20 [R] B,H,W 00000000 00000000 Reserved Reserved Reserved MSGVAL20 [R] B,H,W 00000000 00000000 Reserved Reserved Reserved MSGVAL10 [R] B,H,W 00000000 00000000 INTPND10 [R] B,H,W 00000000 00000000
Block
CAN 0 status flag
Reserved CTRLR1 [R/W] B,H 00000000 00000001 ERRCNT1 [R] B,H,W 00000000 00000000 INTR1 [R] B,H,W 00000000 00000000 BRPE1 [R/W] B,H,W 00000000 00000000 IF1CREQ1 [R/W] B,H 00000000 00000001 IF1MSK21 [R/W] B,H,W 11111111 11111111 IF1ARB21 [R/W] B,H,W 00000000 00000000 IF1MCTR1 [R/W] B,H,W 00000000 00000000 IF1DTA11 [R/W] B,H,W 00000000 00000000 IF1DTB11 [R/W] B,H,W 00000000 00000000 STATR1 [R/W] B,H 00000000 00000000 BTR1 [R/W] B,H,W 00100011 00000001 TESTR1 [R/W] B,H,W 00000000 X0000000 Reserved IF1CMSK1 [R/W] B,H 00000000 00000000 IF1MSK11 [R/W] B,H,W 11111111 11111111 IF1ARB11 [R/W] B,H,W 00000000 00000000 Reserved IF1DTA21 [R/W] B,H,W 00000000 00000000 IF1DTB21 [R/W] B,H,W 00000000 00000000 (Continued) CAN 1 IF 1 register CAN 1 control register
47
MB91460 Series
Address 00C128H to 00C12CH 00C130H 00C134H 00C138H to 00C13CH 00C140H 00C144H 00C148H 00C14CH 00C150H 00C154H 00C158H to 00C15CH 00C160H 00C164H 00C168H to 00C17CH 00C180H 00C184H 00C188H 00C18CH
Register 0 1 Reserved IF1DTA21 [R/W] B,H,W 00000000 00000000 IF1DTB21 [R/W] B,H,W 00000000 00000000 Reserved IF2CREQ1 [R/W]B,H 00000000 00000001 IF2MSK21 [R/W]B,H,W 11111111 11111111 IF2ARB21 [R/W]B,H,W 00000000 00000000 IF2MCTR1 [R/W]B,H,W 00000000 00000000 IF2DTA11 [R/W]B,H,W 00000000 00000000 IF2DTB11 [R/W]B,H,W 00000000 00000000 Reserved IF2DTA21 [R/W]B,H,W 00000000 00000000 IF2DTB21 [R/W]B,H,W 00000000 00000000 Reserved TREQR21 [R]B,H,W 00000000 00000000 Reserved Reserved Reserved TREQR11 [R]B,H,W 00000000 00000000 IF2DTA11 [R/W]B,H,W 00000000 00000000 IF2DTB11 [R/W]B,H,W 00000000 00000000 IF2CMSK1 [R/W]B,H 00000000 00000000 IF2MSK11 [R/W]B,H,W 11111111 11111111 IF2ARB11 [R/W]B,H,W 00000000 00000000 Reserved IF2DTA21 [R/W]B,H,W 00000000 00000000 IF2DTB21 [R/W]B,H,W 00000000 00000000 IF1DTA11 [R/W] B,H,W 00000000 00000000 IF1DTB11 [R/W] B,H,W 00000000 00000000 2 3
Block
CAN 1 IF 1 register
CAN 1 IF 2 register
CAN 1 status flag
(Continued) 48
MB91460 Series
Address 00C190H 00C194H 00C198H 00C19CH 00C1A0H 00C1A4H 00C1A8H 00C1ACH 00C1B0H 00C1B4H 00C1B8H 00C1BCH 00C1C0H to 00C1FCH 00F000H to 00FFFCH 010000H to 013FFCH 014000H to 017FFCH 018000H to 01BFFCH 01C000H to 01FFFCH
Register 0 1 2 3 NEWDT21 [R]B,H,W 00000000 00000000 Reserved Reserved Reserved INTPND21 [R]B,H,W 00000000 00000000 Reserved Reserved Reserved MSGVAL21 [R]B,H,W 00000000 00000000 Reserved Reserved Reserved MSGVAL11 [R]B,H,W 00000000 00000000 INTPND11 [R]B,H,W 00000000 00000000 NEWDT11 [R]B,H,W 00000000 00000000
Block
CAN 1 status flag
Reserved
Reserved
Reserved
Cache TAG way 1 (010000H to 0107FCH)
Cache TAG way 2 (014000H to 0147FCH) Instruction cache Cache RAM way 1 (018000H to 0187FCH)
Cache RAM way 2 (01C000H to 01C7FCH) (Continued) 49
MB91460 Series
(Continued) Address 020000H to 02FFFCH 030000H to 03FFFCH 040000H to 07FFFCH 080000H to 0BFFFCH 0C0000H to 0FFFF4H 0FFFF8H 0FFFFCH 100000H to 13FFFCH 140000H to 17FFFCH 180000H to 1BFFFCH 1C0000H to 1FFFFCH 200000H to 2FFFFCH 300000H to 3FFFFCH Register 0 1 Reserved 2 3 Block
Reserved
I/D-RAM: 64 Kbytes (instruction access is 0 wait cycle, data access is 1 wait cycle)
I/D-RAM 64 Kbytes
External memory area (256 Kbytes)
External memory area (256 Kbytes)
External bus
External memory area (256 Kbytes) FMV [R] FRV [R] External memory area (256 Kbytes) Reset vector/ mode vector
External memory area (256 Kbytes)
External memory area (256 Kbytes) External bus External memory area (256 Kbytes)
External memory area (1 Mbyte)
External memory area (1 Mbyte)
*1 : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes. *2 : ACR0[11:10] depends on the mode vector fetch information on bus width. *3 : TCR[3:0] INIT value = 0000, the value is kept after RST.
50
MB91460 Series
INTERRUPT SOURCE TABLE
Interrupt source Interrupt number
Decimal
Interrupt level Offset
Register address
Setting Hexadecimal register
TBR default Resource address number*1 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 2 3 (Continued) 51
Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 External interrupt 8 External interrupt 9 External interrupt 10 External interrupt 11 External interrupt 12 External interrupt 13 External interrupt 14 External interrupt 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
15 (F) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07
15 (F) fixed 440H 441H 442H 443H 444H 445H 446H 447H
3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H
MB91460 Series
Interrupt source
Interrupt number
Decimal
Interrupt level Offset
Register address
Setting Hexadecimal register
TBR default Resource address number*1 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 4 5 6 7 8 9 (Continued)
Reload timer 0 Reload timer 1 Reload timer 2 Reload timer 3 System reserved System reserved System reserved Reload timer 7 Free-run timer 0 Free-run timer 1 Free-run timer 2 Free-run timer 3 System reserved System reserved System reserved System reserved CAN0 CAN1 System reserved System reserved System reserved System reserved LIN-USART 0 RX LIN-USART 0 TX LIN-USART 1 RX LIN-USART 1 TX LIN-USART 2 RX LIN-USART 2 TX LIN-USART 3 RX LIN-USART 3 TX System reserved Delay interrupt
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23*3
448H 449H 44AH 44BH 44CH 44DH 44EH 44FH 450H 451H 452H 453H 454H 455H 456H 457H
37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H
52
MB91460 Series
Interrupt source
Interrupt number
Decimal
Interrupt level Offset
Register address
Setting Hexadecimal register
TBR default Resource address number*1 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH 000FFEB8H 000FFEB4H 000FFEB0H 000FFEACH 000FFEA8H 000FFEA4H 000FFEA0H 000FFE9CH 000FFE98H 000FFE94H 000FFE90H 000FFE8CH 000FFE88H 000FFE84H 000FFE80H 10 11 12 13 (Continued)
System reserved*2 System reserved*2 LIN-USART 4 RX LIN-USART 4 TX LIN-USART 5 RX LIN-USART 5 TX LIN-USART 6 RX LIN-USART 6 TX System reserved System reserved I2C_0/I2C_2 I C_1/I C_3 System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Input capture 0 Input capture 1 Input capture 2 Input capture 3
2 2
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
(ICR24) ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39
458H 459H 45AH 45BH 45CH 45DH 45EH 45FH 460H 461H 462H 463H 464H 465H 466H 467H
2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH 2B8H 2B4H 2B0H 2ACH 2A8H 2A4H 2A0H 29CH 298H 294H 290H 28CH 288H 284H 280H
53
MB91460 Series
Interrupt source
Interrupt number
Decimal
Interrupt level Offset
Register address
Setting Hexadecimal register
TBR default Resource address number*1 000FFE7CH 000FFE78H 000FFE74H 000FFE70H 000FFE6CH 000FFE68H 000FFE64H 000FFE60H 000FFE5CH 000FFE58H 000FFE54H 000FFE50H 000FFE4CH 000FFE48H 000FFE44H 000FFE40H 000FFE3CH 000FFE38H 000FFE34H 000FFE30H 000FFE2CH 000FFE28H 000FFE24H 000FFE20H 000FFE1CH 000FFE18H 000FFE14H 000FFE10H 000FFE0CH 000FFE08H 000FFE04H 000FFE00H 15 (Continued)
System reserved System reserved System reserved System reserved Output compare 0 Output compare 1 Output compare 2 Output compare 3 System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved
96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47*3 ICR48 ICR49 ICR50 ICR51 ICR52 ICR53 ICR54 ICR55
468H 469H 46AH 46BH 46CH 46DH 46EH 46FH 470H 471H 472H 473H 474H 475H 476H 477H
27CH 278H 274H 270H 26CH 268H 264H 260H 25CH 258H 254H 250H 24CH 248H 244H 240H 23CH 238H 234H 230H 22CH 228H 224H 220H 21CH 218H 214H 210H 20CH 208H 204H 200H
54
MB91460 Series
(Continued) Interrupt source Interrupt number
Decimal
Interrupt level Offset
Register address
Setting Hexadecimal register
TBR default Resource address number*1 000FFDFCH 000FFDF8H 000FFDF4H 000FFDF0H 000FFDECH 000FFDE8H 000FFDE4H 000FFDE0H 000FFDDCH 000FFDD8H 000FFDD4H 000FFDD0H 000FFDCCH 000FFDC8H 000FFDC4H 000FFDC0H 000FFDBCH 000FFDB8H : 000FFC00H 14
System reserved System reserved System reserved System reserved Real-time clock System reserved A/D converter 0 System reserved System reserved System reserved System reserved System reserved Time base overflow PLL clock gear DMA controller Main/sub oscillation stabilization wait System reserved Used by INT instruction
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 : 255
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 : FF
ICR56 ICR57 ICR58 ICR59 ICR60 ICR61 ICR62 ICR63
478H 479H 47AH 47BH 47CH 47DH 47EH 47FH
1FCH 1F8H 1F4H 1F0H 1ECH 1E8H 1E4H 1E0H 1DCH 1D8H 1D4H 1D0H 1CCH 1C8H 1C4H 1C0H 1BCH 1B8H : 000H
*1 : The peripheral resources to which RN (Resource Number) is assigned are capable of being DMA transfer activation sources. In addition, RN has a one-to-one correspondence with an IS (Input Source) of the DMAC channel control register A(DMACA0 to DMACA4), and the IS (Input Source) can be obtained by representing RN in a binary number and adding "1" to the head of it. *2 : Used by REALOS *3 : ICR23 and ICR47 are interchangeable by setting REALOS bit (address 0C03H ISO[0]).
55
MB91460 Series
ELECTRICAL CHARACTERISTICS
1. Absolute maximum rating
Parameter Power supply voltage 1*1 Power supply voltage 2*1 Analog power supply voltage* Analog power supply voltage* Input voltage 1*1 Input voltage 2*1 Analog pin input voltage* Output voltage 1*
1 1 1 1
Symbol VCC3 VCC5 AVCC3 AVRH VI1 VI2 VIA VO1 VO2 ICLAMP ICLAMP IOL IOLAV IOL IOLAV IOL IOHAV IOH IOHAV PD TA Tstg
Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 - 40 - 55 Max VSS + 4.0 VSS + 6.0 VSS + 4.0 VSS + 4.0 VCC3 + 0.3 VCC5 + 0.3 AVCC3 + 0.3 VCC3 + 0.3 VCC3 + 0.3 + 2.0 20 10 8 100 50 - 10 -4 - 50 - 20 1000 + 85 + 125
Unit V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C
Remarks
*2 *2
Output voltage 2*1 Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operation temperature Storage temperature
*6 *6 *3 *4 *5 *3 *4 *5
*1 : The parameter is based on VSS = AVSS = 0.0 V. *2 : Do not let AVCC3 and AVRH exceed VCC+0.3 [V], for example, when the power is turned on. Also, do not let AVCC3 exceed VCC3. *3 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4 : Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. *5 : Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. (Continued)
56
MB91460 Series
(Continued) *6 : * * * * * * * * * * * Corresponding pins: Pin number 2, 3, 116, 117, 120 to 125, 134 to 145, 148 to 160, 163 to 175 Use within recommended operating conditions. Use at DC voltage (current). The +B signal is an input signal exceeding VCC voltage. The +B signal should always be applied by connecting a limiting resistor between the +B signal and the microcontroller. The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the +B signal is input. Note that when the microcontroller drive current is low, such as in the low power consumption modes, the +B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the pin, the microcontroller may operate incompletely. Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power supply voltage may become the voltage at which a power-on reset does not work. Do not leave +B input pin open. Note that analog input/output pins cannot accept +B signal input. Example of recommended circuit :
* Input/output equivalent circuit Protective diode
VCC
Limiting resistor +B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
57
MB91460 Series
2. Recommended operating conditions
(VSS = AVSS = 0.0 V) Parameter Symbol VCC5 Power supply voltage VCC3 AVCC3 Value Min 4.5 3.0 3.0 Typ 4.7 (accuracy within 50%) Max 5.5 3.6 3.6 Unit V V V Use a ceramic capacitor or a capacitor having the similar frequency characteristic. For a smoothing capacitor of VCC pin, use one having a capacitance value greater than CS. Remarks
Smoothing capacitor
CS
F
Operating temperature
TA
- 40
+ 85
C
WARNING: : The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
C_1
C_2
VSS CS
AVSS CS
58
MB91460 Series
3. DC characteristics
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Symbol Pin name P14_0 to P14_3, P15_0 to P15_3, P16_7, P17_0 to P17_7, P18_0 to P18_2, P19_0 to P19_2, P19_4 to P19_6, P20_0 to P20_2, P20_4 to P20_6, P21_0 to P21_2, P21_4 to P21_6, P22_0, P22_2, P22_3, P23_0 to P23_4, P23_6, P24_0 to P24_3, P24_6, P24_7, P28_0 to P28_4, P29_0 to P29_7, NMI, BREAK, MD0 to MD3 P14_0 to P14_3, P15_0 to P15_3, P16_7, P17_0 to P17_7, P18_0 to P18_2, P19_0 to P19_2, P19_4 to P19_6, P20_0 to P20_2, P20_4 to P20_6, P21_0 to P21_2, P21_4 to P21_6, P22_0, P22_2, P22_3, P23_0 to P23_4, P23_6, P24_0 to P24_3, P24_6, P24_7, P28_0 to P28_4, P29_0 to P29_7, D16 to D31, DREQ0, RDY, BRQ, ICD0 to ICD3 P22_4 to P22_7, P24_4, P24_5 Condition Value Min Typ Max Unit Remarks
VIH1
0.8 x VCC
VCC + 0.3
V
CMOS hysteresis input*1
"H" level input voltage
VIH2
0.7 x VCC
VCC + 0.3
V
CMOS input*1
VIH3
0.7 x VCC
VCC5 + 0.3
V
I2C input*2 (Continued) 59
MB91460 Series
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Symbol Pin name P14_0 to P14_3, P15_0 to P15_3, P16_7, P17_0 to P17_7, P18_0 to P18_2, P19_0 to P19_2, P19_4 to P19_6, P20_0 to P20_2, P20_4 to P20_6, P21_0 to P21_2, P21_4 to P21_6, P22_0, P22_2, P22_3, P23_0 to P23_4, P23_6, P24_0 to P24_3, P24_6, P24_7, P28_0 to P28_4, P29_0 to P29_7, NMI, BREAK, MD0 to MD3 P14_0 to P14_3, P15_0 to P15_3, P16_7, P17_0 to P17_7, P18_0 to P18_2, P19_0 to P19_2, P19_4 to P19_6, P20_0 to P20_2, P20_4 to P20_6, P21_0 to P21_2, P21_4 to P21_6, P22_0, P22_2, P22_3, P23_0 to P23_4, P23_6, P24_0 to P24_3, P24_6, P24_7, P28_0 to P28_4, P29_0 to P29_7, D16 to D31, DREQ0, RDY, BRQ, ICD0 to ICD3 P22_4 to P22_7, P24_4, P24_5 Condition Value Min Typ Max Unit Remarks
VIL1
VSS-0.3
0.2 x VCC
V
CMOS hysteresis input*1
"L" level input voltage
VIL2
VSS-0.3
0.3 x VCC
V
CMOS input*1
VIL3
VSS-0.3
0.3 x VCC3
V
I2C input*2 (Continued)
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MB91460 Series
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Symbol Pin name P14_0 to P14_3, P15_0 to P15_3, P17_0 to P17_3, P18_0 to P18_2, P19_0 to P19_2, P19_4 to P19_6, P20_0 to P20_2, P20_4 to P20_6, P21_0 to P21_2, P21_4 to P21_6, P22_0, P22_2, P22_3, P23_0 to P23_4, P23_6, P24_0 to P24_3, P24_6, P24_7 P16_7, P17_4 to P17_7, P28_0 to P18_4, P29_0 to P19_7, D16 to D31, ICD0 to ICD3, A00 to A23, AS, BGRNT, CS0 to CS4, DACK0, DEOP0, ICLK, ICS0 to ICS2, IORD, IOWR, RD, SYSCLK, WDRESET, WR0, WR1 Condition Value Min Typ Max Unit Remarks
VOH1
VCC = 5.0 V, IOH = 4.0 mA/ VCC = 3.3 V, IOH = 2.0 mA
VCC-0.5
V
3.3 V, 5 V switch pin*3
"H" level output voltage
VOH2
VCC3 = 3.3 V, IOH = 4.0 mA
VCC3-0.5
V
3.3 V dedicated pin
(Continued)
61
MB91460 Series
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Symbol Pin name P14_0 to P14_3, P15_0 to P15_3, P17_0 to P17_3, P18_0 to P18_2, P19_0 to P19_2, P19_4 to P19_6, P20_0 to P20_2, P20_4 to P20_6, P21_0 to P21_2, P21_4 to P21_6, P22_0, P22_2, P22_3, P23_0 to P23_4, P23_6, P24_0 to P24_3, P24_6, P24_7 P16_7, P17_4 to P17_7, P28_0 to P28_4, P29_0 to P29_7, D16 to D31, ICD0 to ICD3, A00 to A23, AS, BGRNT, CS0 to CS4, DACK0, DEOP0, ICLK, ICS0 to ICS2, IORD, IOWR, RD, SYSCLK, WDRESET, WR0, WR1 P22_4 to P22_7, P24_4, P24_5 All input pins Condition Value Min Typ Max Unit Remarks
VOL1
VCC = 5.0 V, IOL = 4.0 mA/ VCC = 3.3 V, IOL = 2.0 mA
0.4
V
3.3 V, 5 V switch pin*3
"L" level output voltage
VOL2
VCC3 = 3.3 V, IOL = 4.0 mA
0.4
V
3.3 V dedicated pin
VOL3 Input leak current Pull-up resistance value Pull-down resistance value
VCC3 = 3.3 V, IOL = 3.0 mA VCC = DVCC = AVCC = 5.0 V, VSS < VI < VCC
-5

0.4 +5
V A
I2C output
IIL
PUP
INIT, pull-up pin
25
50
100
k
PDOWN
INIT, pull-up pin
25
50
100
k (Continued)
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MB91460 Series
(Continued) (VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Symbol Pin name Condition CPU core : 80 MHz, External bus : 40 MHz (no-load) Peripheral macro : 10 MHz CAN : 20 MHz TA = + 85 C TA = + 85 C f = 1 MHz Value Min Typ Max Unit Remarks
Parameter
ICC3 Power supply current ICC5 ICCH
VCC3
120
150
mA
VCC5 VCC3 VCC3 Except VCC3, VCC5, VSS, AVCC, AVSS, AVRH
15 1 10
20 3 50
mA mA At stop A pF At shutdown
Input capacitance
CIN
5
15
*1 : For a pin which can select the I/O power supply between 3.3 V and 5 V, the value is based on the power supply voltage currently used. Although 5 V input is possible for TRST, the input becomes CMOS hysteresis based on the input threshold value VCC3. *2 : Although 5 V input is possible for I2C pin, the input is made based on the input threshold value VCC3. *3 : For a pin which can select the I/O power supply between 3.3 V and 5 V, the drive capability changes depending on the power supply voltage.
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MB91460 Series
4. AC characteristics
(1) Clock timing (VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Clock frequency Clock cycle time Symbol fC tC fCP Internal operation clock frequency fCPP fCPT fCAN tCP Internal operation clock cycle time tCPP tCPT tCAN Pin Conname dition X0 X1 X0 X1 Value Min 10 50 4.6 4.6 4.6 12.5 50 26.7 50 54 100 80 20 40 20 217 217 217 ns MHz CPU MHz Peripheral MHz External bus MHz ns ns ns ns Clock after divided by CAN prescaler CPU Peripheral External bus Clock after divided by CAN prescaler Typ 18.5 Max 20 Unit MHz Remarks
Note : These values are assumed based on the division setting of each clock set to 16. * Conditions for measuring the clock timing ratings
tC
Output pin
0.8 VCC 0.2 VCC C = 50 pF
PWH
PWL
64
MB91460 Series
(2) Clock output timing (VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Cycle time SYSCLKSYSCLK SYSCLKSYSCLK Symbol Pin name tCYC tCHCL tCLCH SYSCLK SYSCLK SYSCLK Condition Value Min tCPT 12.5 12.5 Max 108.5 108.5 Unit ns ns ns * Remarks
* : tCYC is the frequency of 1 clock cycle.
tCYC tCHCL tCLCH
VOH
VOH VOL
SYSCLK
(3) Reset input ratings (VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter INIT input time (at power-on, at return from shutdown mode) INIT input time (other than the above) Symbol Pin name Condition Value Min 8 tINTL INIT 20 s Max Unit
ms
tINTL
INIT
0.2 VCC
65
MB91460 Series
(4) Normal bus access read/write operation (VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter CS0 to CS4 setup CS0 to CS4 hold Symbol tCSLCH tCSDLCH tCHCSH tASCH Address setup tASWL tASRL tCHAX Address hold tWHAX tRHAX Valid address/valid data input time WR0, WR1 delay time Data setup time (WRn rising) Data hold time (WRn rising) WR0, WR1 minimum pulse width RD delay time Data setup time (RD rising) Data hold time (RD rising) RD minimum pulse width AS setup AS hold tAVDV tCHWL tCHWH tDSWH tWHDX tWLWH tCHRL tCHRH tDSRH tRHDX tRLRH tASLCH tCHASH SYSCLK A23 to A00 WR0, WR1 A23 to A00 RD A23 to A00 SYSCLK A23 to A00 WR0, WR1 A23 to A00 RD A23 to A00 A23 to A00 D31 to D16 SYSCLK WR0, WR1 D31 to D16 WR0, WR1 D31 to D16 WR0, WR1 WR0, WR1 SYSCLK RD D31 to D16 RD D31 to D16 RD RD SYSCLK AS SYSCLK CS0 to CS4 Pin name Condition Value Min 3 -3 3 3 3 3 3 3 3 tCYC - 3 3 tCYC - 3 20 0 tCYC - 3 3 3 Max tCYC/2 + 6 tCYC/2 + 6 3/2 x tCYC - 15 6 6 6 6 tCYC/2 + 6 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *
* : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC x the number of cycles added for the delay) to this rating.
66
MB91460 Series
tCYC VOH BA1 VOH VOH VOH
SYSCLK
tASLCH tCHASH
AS
VOH VOL tCSLCH tCHCSH VOH
CS0 to CS4
VOL
tASCH
tCHAX VOH VOL tCHRH tRLRH VOL VOH tRHAX
A23 to A00
VOH VOL
tCHRL
RD
tASRL
tDSRH tRHDX tAVDV
D31 to D16
VIH
VIH
Read
VIL tCHWL tWLWH tCHWH VIL
WR0, WR1
tASWL
VOL
VOH tWHAX tWHDX tDSWH
D31 to D16
VOH VOL
Write
VOH VOL
67
MB91460 Series
(5) Ready input timing (VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter RDY setup time SYSCLK SYSCLK RDY hold time Symbol tRDYS tRDYH Pin name SYSCLK RDY SYSCLK RDY Condition Value Min 10 0 ns Max Unit ns
tCYC VOH VOH VOL
SYSCLK
VOL
tRDYS tRDYH
tRDYS tRDYH
When RDY wait is applied
VOH VOL VOL
VOH
When RDY wait is not applied
VOH VOL
VOH VOL
68
MB91460 Series
(6) Hold timing (VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter BGRNT delay time BGRNT rising from pin floating BGRNT rising from pin valid Symbol tCHBGL tCHBGH tXHAL tHAHV Pin name SYSCLK BGRNT BGRNT Condition Value Min tCYC - 10 tCYC - 10 Max 10 10 tCYC + 10 tCYC + 10 Unit ns ns ns ns
Note : After a BRQ is captured, a minimum of 1 cycle is required before BGRNT changes.
tCYC
SYSCLK
VOH
VOH
VOH
VOH
BRQ
tCHBGL
tCHBGH VOH tHAHV
BGRNT
tXHAL
VOL
Each pin High impedance
69
MB91460 Series
(7) LIN-UART timing (VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SCK rising time SCK falling time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX tF tR Pin name SCK0 to SCK6 SCK0 to SCK6, SOT0 to SOT6 SCK0 to SCK6, SIN0 to SIN6 SCK0 to SCK6, SIN0 to SIN6 SCK0 to SCK6 SCK0 to SCK6 SCK0 to SCK6, SOT0 to SOT6 SCK0 to SCK6, SIN0 to SIN6 SCK0 to SCK6, SIN0 to SIN6 SCK0 to SCK6 SCK0 to SCK6 External shift clock mode Condition Value Min 5tCYCP - 50 Internal shift clock mode tCYCP + 80 0 tCYCP + 10 3tCYCP 30 tCYCP + 30 Max + 50 150 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns
Notes : * Above values are AC characteristics for CLK synchronous mode. * tCYCP is the cycle time of the peripheral clock.
70
MB91460 Series
* Internal shift clock mode
tSCYC
SCK0 to SCK6
VOL tSLOV VOH VOL
VOH
VOL
SOT0 to SOT6
tIVSH VOH VOL
tSHIX VOH VOL
SIN0 to SIN6
* External shift clock mode
tSLSH tSHSL VOL tSLOV VOH VOL tIVSH VOH VOL tSHIX VOH VOL VOH VOL
SCK0 to SCK6
VOL
SOT0 to SOT6
SIN0 to SIN6
71
MB91460 Series
(8) DMA controller timing (VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter DREQ0 input pulse DACK0 delay time DEOP0 delay time IORD delay time IOWR delay time Symbol tDRWH tCLDL tCLDH tCLEL tCLEH tCHIRL tCHIRH tCHIWL tCHIWH Pin name DREQ0 DACK0 DEOP0 IORD IOWR Condition Value Min Max 10 10 10 10 10 10 10 10 10 Unit ns ns ns ns ns ns ns ns ns
Note : After a BREQ is captured, a minimum of 1 cycle is required before BGRNT changes.
tCYC
SYSCLK
VOH
VOH
VOH
VOH
tCLDL
tCLDH VOL VOH
DACK0
tCLEL
tCLEH VOH VOL
DEOP0
tCHIRL
tCHIRH VOH
IORD
VOL
tCHIWL
tCHIWH
IOWR
VOL
VOH
tDRWH
DREQ0
VOL
VOH
72
MB91460 Series
(9) Free-run timer clock (VCC5 = 4.0 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name FRCK0 to FRCK3 Condition Value Min 4tCYCP Max Unit ns
Note : tCYCP is the cycle time of the peripheral clock.
FRCK0 to FRCK3
tTIWH tTIWL
(10) Trigger input timing (VCC5 = 4.0 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Input capture input trigger A/D converter trigger Symbol tINP tATGX Pin name ICU0 to ICU3 ATG Condition Value Min 5tCYCP 5tCYCP Max Unit ns ns
Note : tCYCP is the cycle time of the peripheral clock.
tATGX, tINP
ICU0 to ICU3, ATG
73
MB91460 Series
5. A/D converter
(1) Electrical characteristics (VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to + 85 C) Parameter Resolution Total error*1 Linearity error*1 Differential linearity error*1 Zero transition voltage*1 Full transition voltage*1 Conversion time Analog port input current Analog input voltage Reference voltage Analog power supply current (analog + digital) Analog input equivalent capacity Analog input equivalent resistance Output impedance of analog signal source Symbol VOT VFST IAIN VAIN IA IAH*3 Cin Rin Rext AVCC3 Pin name Value Min Typ Max 10 3 2.5 1.9 Unit bit LSB LSB LSB LSB LSB s A V V mA A pF k k AVCC3 2.7 V AVCC3 2.7 V Including reference supply At AVCC3 = 3.3 V, AVRH = 3.3 V Remarks
AN0 to AN12 AVRL-1.5 AVRL-0.5 AVRL-2.5 AN0 to AN12 AVRH-3.5 AVRH-1.5 AVRH-0.5 AN0 to AN12 AN0 to AN12 AVRH 1 *2 AVSS AVSS 1.5 10 AVRH AVCC3 2.5 10 14.7 1.9 1.9
AN0 to AN12 AN0 to AN12
*1 : Measured in the CPU sleep state *2 : Set the peripheral clock and conversion time setting register to set a time equal to or longer than this time. *3 : The current when A/D converter is not operating, or in the CPU stop mode (at VCC3 = AVCC3 = AVRH = 3.3 V).
74
MB91460 Series
(2) Cautions Relating to the A/D Converter The diagram below shows the equivalent circuit of the sampling circuit in the A/D converter. The output impedance of the external circuit connected to the analog input must satisfy the following criteria. * The recommended output impedance for the external circuit is 1.9 k or less. * If an external capacitor is used, remember to consider the capacitive voltage divider effect due to the external capacitor and the internal capacitor in the chip. Accordingly, an external capacitance several thousand times that of the internal capacitance is recommended. * The analog voltage sampling period may be too short if the output impedance of the external circuit is high. In this case, select Rext and Tsamp such that they satisfy the following condition. Rext = Tsamp/ (7 x Cin) - Rin Rext Tsamp Cin Rin : Output impedance of the analog signal source : Sampling time : Equivalent capacitance of analog input : Equivalent resistance of analog input
* Input impedance
Analog input pin Analog SW Rin:1.9 k (Max)
Analog signal source
Rext
Cin:14.7 pF (Max)
A/D converter
Device internal circuit
75
MB91460 Series
(3) Definition of A/D converter terms * Resolution Analog variation that is recognizable by an A/D converter. * Linearity error Deviation between actual conversion characteristics and a straight line connecting zero transition point (00 0000 0000 00 0000 0001) and full scale transition point (11 1111 1110 11 1111 1111). * Differential linearity error Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. * Total error This error indicates the difference between actual and theoretical values, including the zero transition error/ full scale transition error/linearity error.
Total error
3FFH 3FEH 1.5 LSB
Digital output
3FDH
Actual conversion characteristics
{1 LSB (N - 1) + 0.5 LSB}
004H
VNT
003H 002H 001H 0.5 LSB' AVSS AVRH
(measurement value) Actual conversion characteristics
Ideal characteristics
Analog input
1LSB' (ideal value) = AVRH - AVSS 1024
[V]
Total error of digital output N = VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB' N : A/D converter digital output value VOT' (ideal value) = AVSS + 0.5 LSB' [V] VFST' (ideal value) = AV - 1.5 LSB' [V] VNT : A voltage at which digital output transits from (N + 1) H to NH
76
MB91460 Series
Linearity error
3FFH 3FEH {1 LSB (N - 1) + VOT} 3FDH
Actual conversion characteristics
Differential linearity error
Actual conversion characteristics
(N+1)H
VFST
Digital output
Digital output
(measurement value)
Ideal characteristics
NH
004H 003H 002H 001H
VNT
(measurement value)
(N-1)H
VFST VNT
(measurement value)
Actual conversion characteristics
(measurement value)
Ideal characteristics
(N-2)H
VTO (measurement value)
AVSS AVRH AVSS
Actual conversion characteristics
AVRH
Analog input
Analog input
Linearity error of digital output N =
VNT - {1LSB x (N - 1) + VOT} [LSB] 1LSB
Differential linearity error of digital output N = V (N + 1) T - VNT [LSB] 1LSB 1LSB = VFST - VOT 1022 [V]
N : A/D converter digital output value VOT : A voltage at which digital output transits from 000H to 001H. VFST : A voltage at which digital output transits from 3FEH to 3FFH.
77
MB91460 Series
ORDERING INFORMATION
Part number MB91461PMC-GSE1 Package 176-pin, plastic LQFP (FPT-176P-M07) Remarks Lead-free package
78
MB91460 Series
PACKAGE DIMENSION
176-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.50 mm 24.0 x 24.0 mm Gullwing Plastic mold 1.70 mm MAX P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP (FPT-176P-M07)
26.000.20(1.024.008)SQ *24.000.10(.945.004)SQ
Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
132
89
133
88
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0~8
0.100.10 (.004.004) (Stand off)
INDEX 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010)
176
45
"A" LEAD No.
1 44
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
C
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
79
MB91460 Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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